Semiconductor circuitry system with functionality of conversion between digital and analog domains is essential for modern electronic, e.g., mobile phone, notebook/tablet computer, digital camera/camcorder, navigation system, etc.
For converting a digital input to an analog output, a DAC (digital-to-analog converter) selectively activates a subset of a plurality of conversion elements (e.g., resistors, capacitors or current sources, etc.) according to value of the digital input, so as to synthesize the analog output. However, the plurality of conversion elements suffer deviations (e.g., variations) from their expected values, and therefore introduce mismatch error during conversion. Some kinds of ADCs (analog-to-digital converters) also adopt conversion elements and/or utilize internal DACs to perform analog-to-digital conversion. Therefore, suppressing mismatch error is important for both DAC and ADC.
Please refer to FIG. 1 illustrating a prior art DAC system 100 which converts a digital input Di of (Ma+Mb) bits to an analog output Vop. The DAC system 100 includes a digital first-order modulator 102 (e.g., a sigma-delta modulator), two DEM (dynamic element matching) circuits 104a and 104b, and two DACs 106a and 106b. The digital first-order modulator 102 modulates the digital input Di to a digital signal Da of Ma bits, and the digital signal Da includes the digital input Di and the quantization error of the digital modulator 102. The DAC 106a includes a plurality of equal weighted conversion elements (not shown) for converting the digital signal Da to an analog signal Va. During conversion of the digital signal Da, the digital signal Da is coded from binary code to thermometer code, and the DEM circuit 104a selects a number of the conversion elements of the DAC 106a with the number determined according to the digital value Da, so the DAC 106a generates the analog signal Va by the selected conversion elements.
On the other hand, the digital signal Da is subtracted from the digital input Di to form another digital signal Db, and the digital signal Db reflects the quantization error of the digital modulator 102. The DAC 106b includes a plurality of equal weighted conversion elements (not shown) for converting the digital signal Db to an analog signal Vb. During conversion of the digital signal Db, the digital signal Db is coded from binary code to thermometer code, and the DEM circuit 104b selects a number of the conversion elements of the DAC 106b with the number determined according to the digital value Db, so the DAC 106b generates the analog signal Vb by the selected conversion elements. The analog signal Vb is subtracted from the analog signal Va to form the analog output Vop.
The DAC system 100 has some disadvantages. To convert the digital input Di, the DAC system 100 needs to concurrently receive all bits of the digital input Di. The DAC system 100 is therefore not applicable for successive bit-by-bit digital-to-analog conversion, such as the DAC utilized in SAR (successive approximation register) ADC. In addition, the DAC system 100 suffers delay caused by the digital first-order modulator 102. Consequently, the DAC system 100 is not applicable for fast conversion, such as CT-DSM (continuous time delta sigma modulator).